Wafer scale thin film package

ABSTRACT

A chip module having a chip with a flexible multilayer redistribution thin film attached thereto for connection to a substrate. The thin film acts as both a redistribution medium with multiple layers of redistribution metallurgy for chip power and signals and as a compliant medium to relieve stresses caused by thermal expansion mismatch between chip and substrate. Modules comprising chip and thin film may be fabricated at the chip or wafer level. The upper surface of the thin film has an array of pads matching the array of pads on the chip or wafer while the lower surface has pads matching those of the substrate. The multilayer thin film is first formed on a temporary substrate and then the chip is attached to the thin film before release from the temporary substrate. After release, the module is ready for mounting to the second level packaging substrate, such as a chip carrier or PCB. Where the multilayer thin film is formed directly on a wafer, the wafer is then diced to form the module.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to electronic packaging and methodsof fabricating same. More particularly, the present invention relates tosemiconductor chip packaging using a multilayer thin film for chipattachment to a substrate.

[0003] 2. Background and Related Art

[0004] Ever increasing industry demand for smaller and smallerelectronic packages with low profile, higher area density and increasingnumber of input/output connections (I/Os) has led to increasing demandfor the Chip Scale Package (CSP). Use of such packages may be found insmall portable products, such as cellular phones, pagers, and the like.However, it is known that CSPs have somewhat limited applicationsbecause of the limited number of I/Os due to solder interconnectreliability constraints. As feature sizes of the semiconductor chippackages decrease, as in the case of CSPs, and the I/O connection countincreases, so too will the number of chips packaged in a given area.This will increase the heat dissipated by each of the chips which will,in turn, increase the thermal mismatch stresses between chip andsubstrate, the latter of which will decrease the interconnectreliability of the package. Various efforts have been made in the priorart to address the thermal mismatch problem. In addition, variousefforts have been made to improve interconnect reliability and reducecost by, for example, fabricating CSPs at the wafer level. However,these efforts have not been totally successful and have involvedrelatively complex and costly assemblies with limited capability.

[0005] In view of the limitations of prior art chip packaging mentionedhereinabove, there continues a need for a relatively simple, lowprofile, high density, chip packaging approach which has highinterconnect reliability and high I/O connection count, and which mayuse relatively low-cost wafer scale processing.

SUMMARY OF THE INVENTION

[0006] In accordance with the principles of the present invention, arelatively simple chip packaging approach is provided using multilayerthin film technology. The flexible thin film acts as both aredistribution layer and a stress relief layer between chip and secondlevel interconnect substrate. More particularly, the flexible multilayerthin film acts to provide multiple layers of redistribution metallurgyfor both power and signals in the X-Y plane (e.g. fanout or grid change)and also provides sufficient flexibility to connections in both theZ-direction and X-Y plane to relieve stresses caused by the thermalexpansion mismatch between semiconductor chip and second levelinterconnect substrate, such as, a PCB.

[0007] The flexible multilayer thin film is first mounted on either asilicon die or wafer. The upper surface of the thin film has an array ofpads matching the array of pads on the die or wafer while the lowersurface has pads matching those of the second level interconnectsubstrate. The mounting of the multilayer thin film on a die creates amodule for mounting to the second level substrate, such as a chipcarrier or PCB. Where the multilayer thin film is formed directly on awafer, the wafer is then diced to form the modules.

[0008] Accordingly, it is an object of the present invention to providean improved semiconductor chip package and method for making same.

[0009] It is a further object of the present invention to provide a chippackage having a flexible multilayer redistribution thin film attachedthereto to form a low profile, low vertical inductance, module.

[0010] It is yet a further object of the present invention to provide achip module comprising a flexible multilayer thin film attached to thechip which thin film acts as both a redistribution medium and stressrelief medium between chip and next level of packaging.

[0011] It is another object of the present invention to provide a chipmodule formed by fabricating a flexible multilayer redistribution thinfilm on a wafer before dicing.

[0012] It is yet another object of the present invention to provide achip package and method of making same which acts to increaseinterconnection reliability and I/O count and provide simple, low cost,assembly.

[0013] These foregoing and other objects, features and advantages of theinvention will be apparent from the following more particulardescription of a preferred embodiment of the invention, as illustratedin the accompanying drawings, wherein like reference members representlike parts of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

[0014]FIG. 1 shows a cross-section of a partially assembled chip module,made in accordance with the present invention.

[0015]FIG. 2 shows a cross-section of a partially assembled chip packagemade in accordance with the present invention.

[0016]FIG. 3a shows a cross-section of an assembled chip package, madein accordance with the present invention.

[0017]FIG. 3b shows an exploded view of a portion of the chip packageshown in FIG. 3a.

[0018]FIG. 4 shows a cross-sectional view of an alternative embodimentof the chip package shown in FIG. 3a.

[0019]FIG. 5 shows another embodiment of the chip package in accordancewith the present invention.

[0020]FIG. 6a shows a further embodiment wherein the flexible multilayerredistribution thin film is first fabricated on a wafer.

[0021]FIG. 6b shows a cross-section of the thin-film-on-wafer of FIG.6a.

[0022]FIG. 6c shows an exploded view of the cross-section of FIG. 6b.

DETAILED DESCRIPTION

[0023] With reference to FIG. 1, there is shown a cross-sectional viewof a partially assembled chip module which view is used to facilitate adescription of the process for creating the flexible multilayerredistribution thin film and attaching to a chip, in accordance with thepresent invention. Multilayer thin film 1 is first formed upon masterglass substrate 3. The thin film may be formed by any of a variety ofthin film lithography techniques known to those skilled in the art.

[0024] Fabrication of the thin film structure using conventionallithographic processing steps necessarily begins with selecting a flat,rigid substrate to ensure good feature resolution. For ease of removalof the thin film after completion of its formation, glass has beenselected. To reduce thermal expansion mismatch between the chip andglass substrate 3, a glass with a CTE similar to silicon is selected,such as a Boro float glass. The glass surface for deposit may first becleaned and then a thin release layer 8 microns thick is deposited. Therelease layer (not shown) is typically the same material as is used toform the thin film structure and may be deposited by spinning onto glasssubstrate 3. For example, a polymer, such as, polyimide may be used. Thepolymer release layer is then properly cured. Pads 5 may then be formedon the substrate or, alternatively, formed after the module iscompleted. Where pads 5 are formed at this point, they are formed in apattern matching the pattern of the second level package to which it isto be attached. The pads may be BGA pads, for example, formed bysputtering or electroplating, for example, 10-20 microns of metal, suchas copper.

[0025] A first layer of polyimide (or other polymer such as a filledPTFE or Teflon®, Teflon® is a registered trademark of E. I. du Pont deNemours & Company) 10-11 microns thick is then spun onto the releaselayer with or without pads, depending upon process choice. A pattern ofvias selected according to the pattern of pads formed on the glasssubstrate matching the pads on the second level package to which it willbe attached, is then ablated by laser ablation into the first layer ofpolyimide. The vias are then filled with conductive material to theunderlying pads. This may be done by electroplating copper to the copperpads or filling with an electrically conductive adhesive. It is clearthat other metals may also be used instead of copper. Where pads havenot yet been formed, the vias may be electrolessly plated with copper.

[0026] A layer of copper is then deposited on the first layer ofpolyimide and in contact with the conductively filled vias. The layer ofcopper may be 5-6 microns thick and can be electroplated. The layer ofcopper is then masked with a layer of resist according to the selectedmetallurgical pattern of the overall redistribution pattern to leavecopper lines contacting selected vias. The layer of copper is thenetched, for example, by reactive ion etching. Then a second layer ofpolyimide is deposited upon the first layer of polyimide and copperlines. A pattern of vias is then ablated into the second layer ofpolyimide at selected locations to the underlying copper lines and thevias are plated with copper. Another layer of copper is then depositedupon the second layer of polyimide and copper plated vias. The secondlayer of copper is etched according to the desired metallurgical patternand the process repeats until the overall redistribution pattern isachieved.

[0027] When the final layer of polyimide is formed, the pattern of metalfilled vias is selected to match the pattern of conductive pads (notshown) on chip 7. Pads are then formed on these vias. Such pad may be,for example, C4 pads. FIG. 3b shows a typical 3 level redistributionthin film. It is clear that any desired number of layers of polyimideand metal may be employed, depending upon the complexity of theredistribution pattern. It is also clear that any of a variety ofdeposition and etching techniques may be employed to form the layers ofmaterial, vias and metallurgical patterns.

[0028] Again, with reference to FIG. 1, after forming the multilayerredistribution thin film on substrate 3 with a pattern of C4 pads on itstop surface matching the pattern of pads on chip 7, high melt C4 solderballs 9, for example, are attached to the pads, as shown. Chip 7 is thenpositioned and attached by C4 melting of the high melt solder, as isknown to those skilled in the art. Other alloy systems may also be usedin place of the high melt solder, such as, eutectic SnPb, SnAgCu orSnAgBi. After attaching chip 7 to thin film 1, the chip is underfilledwith any of a variety of underfills, such as an epoxy, to bond chip 7 tothin film 1. The epoxy may be with or without fillers. Examples of suchepoxies are Hysol, Namics and RCE. The underfill step may be carried outby dispensing with a dispensing needle from the edge of the chip wherethe epoxy will penetrate by capillary action.

[0029] After the underfill step, the resulting module comprising chip 7and thin film 1 is separated from glass substrate 3. This may be done-bylaser ablation, such as, with a 308 nm He—Ne laser. The detached surfaceof the module is then cleaned by etching, and if pads have not beenpreviously formed, to prepare for the formation of the BGA pads. Thesepads may be formed, for example, by ablating a pattern of recesses forthe pad areas and then plating therein a 10-20 micron layer of copper,according to the underlying pattern of vias matching the second levelpackage to which it will be connected.

[0030] After separation from glass substrate 3, the resulting module 11(with chip, C4-s, underfill, thin film and BGA pads) as shown in FIG. 2,is attached to a second level package, such as, PCB 13. PCB 13 is shown,for example, with an array of low temperature melt solder balls 15matching pads 5 on module 11, as hereinabove described. Solder balls 15are formed on BGA pads 16. As described above, other alloy systems mayalso be used in place of the low melt solder, such as, eutectic SnPb,SnAgCu or SnAgBi. Spacer 17 is used for alignment and reinforcement.Examples of such spacers are layers of EKJ (DuPont®) or Kaptong, Kapton®is a registered trademark of E. I. du Pont de Nemours & Company, 150-200microns thick punched or drilled with holes for aligning solder balls 15to pads 5. The spacer not only acts to align but also acts to providestress relief to the solder ball interconnections by redistributingstress due to thermal expansion mismatch. The spacer may be joined tothe thin film redistribution layer and PCB by either a thermoplasticadhesive or adhesive tape. After alignment, the low temperature meltsolder is heated to reflow the solder and make connection of chip moduleto PCB. It is clear that rather than use a spacer to align module 11 toPCB 13, module 11 may be otherwise aligned in contact with solder balls15 and heated to form the connection, and then a reworkable underfilldispensed to support the connection.

[0031] The resulting assembled package is shown in FIG. 3a. An expandedview of a portion of FIG. 3a is shown in FIG. 3b. C4 connections 21 inFIG. 3b are shown separated by underfill 19. For demonstration purposes,a 3 level thin film is shown with via filled conductors 23 and layers ofmetallurgy 25 between the three layers of polyimide 27. It is clear thatmore than 3 levels of thin film may be employed, depending upon thedegree of redistribution required. Spacer 17 surrounds solder connection29, the latter making contact with BGA pads 5 of module 11 and pads 16of PCB 13. Although reference has been made to mounting module 11 on aPCB, it is clear that other carriers may be used, such as an organic orceramic carrier.

[0032]FIG. 4 shows an alternative embodiment of the chip package shownin FIG. 3a. As can be seen, 2 modules 11 are mounted on PCB 13. It isclear that more than 2 modules could be mounted on the PCB.

[0033]FIG. 5 shows a further embodiment where the carrier 31 for modules11 is a substrate mounted on PCB 13. Carrier 31 may be an organic orceramic carrier.

[0034] With reference to FIG. 6, there is shown a further embodimentwherein the flexible multilayer redistribution film is first fabricatedon a wafer. FIG. 6a shows a front view of a wafer upon which individualchip multilayer redistribution thin film 33 patterns are formed. Theindividual patterns of thin film 33 for each chip are as describedabove, for purposes of redistribution of power and signal or grid changein the X-Y plane (parallel to the chip). FIG. 6b shows a cross-sectionof FIG. 6a wherein the individual chip patterns 33 of the overall thinfilm layer 34 are shown respectively formed directly on the array ofchips of wafer 35. FIG. 6c shows an exploded view of FIG. 6b with BGApads 37 shown on the final layer of an individual chip multilayerredistribution thin film. Metallurgical pattern 39 and vias 41, at thecross-section taken, are shown by way of example.

[0035] Fabrication of the overall multilayer thin film on wafer 35 issimilar to that described above for fabrication of the chip level.However, it is clear that via, masking and etching patterns for theindividual chip multilayer redistribution thin films 33 may vary, onefrom the other, or may be the same throughout the wafer. Fabricationdirectly on wafer 35 begins by spinning, for example, a layer ofpolyimide 10 to 11 microns thick onto the wafer covering the array ofchips connection pads (not shown) on the wafer. Vias are then ablated inthe polyimide to expose the array of chip connection pads. The vias arefilled by electroplating, for example, to the chip pads to formconductive columns 41. Typically, copper would be plated to copper pads.Next, a layer of copper is deposited upon the layer of polyimide andcopper filled vias and the process continues, as described above, toform layers of metal 39 of the multilayer metallurgical redistributionpattern. The final layer of polyimide is fabricated with a pattern ofvias on the individual chip multilayer redistribution thin film matchingthe pattern of pads on the PCB to which it will be attached. As a finalstep in fabricating at the wafer level to form a wafer scale package, apattern of BGA pads 37 is formed on the vias which pattern, then,matches the pattern of PCB pads. The wafer may then be diced usingconventional dicing techniques, as is known to those skilled in the art.The resulting module, comprising chip and flexible multilayerredistribution thin film may then be attached to a carrier in thevariety of way described above. It should be noted that whether theflexible multilayer redistribution thin film module is formed at thewafer level, as described with respect to FIG. 6, or at the chip level,as described with respect to FIG. 1, the resulting thin film of themodule can be made, dimensionally, to an area the same size as the chiparea to which it is attached.

[0036] It will be understood from the foregoing description that variousmodifications and changes may be made in the preferred embodiment of thepresent invention without departing from its true spirit. It is intendedthat this description is for purposes of illustration only and shouldnot be construed in a limiting sense. The scope of this invention shouldbe limited only by the language of the following claims.

What is claimed is:
 1. A chip module comprising: a flexibleredistribution thin film having multiple layers of redistributionmetallurgy for redistributing power and signals from chip to a substratetherefor and providing sufficient elasticity to relieve stresses causedby thermal mismatch between chip and substrate, said thin film having apattern of connection points matching the pattern of connection pads onsaid chip and which are electrically connected thereto with said thinfilm attached to said chip so as to form a module for attachment to saidsubstrate.
 2. The module of claim 1 wherein said thin film is made of apolymer.
 3. The module of claim 1 wherein said thin film is electricallyconnected to said chip by solder ball connections and attached byfilling the space between solder ball connections with epoxy.
 4. Thechip module of claim 1 wherein said flexible redistribution thin film isformed directly on said chip to form said chip module.
 5. The chipmodule of claim 1 wherein at least one chip module is attached to saidsubstrate to form a chip package.
 6. The chip package of claim 5 whereinsaid substrate is a chip carrier for attachment to a PCB.
 7. The chippackage of claim 5 where said substrate is a PCB.
 8. A chip packagecomprising: a flexible redistribution thin film having multiple layersof redistribution metallurgy for redistributing power and signals fromchip to substrate and providing sufficient elasticity to relievestresses caused by thermal mismatch between chip and substrate, saidthin film having formed thereon a pattern of connection pads on onesurface matching the pattern of connection pads on said substrate; apattern of connection points formed on the other surface of said thinfilm matching the pattern of connection pads on said chip withrespective ones of said pads on said chip electrically connected torespective ones of said connection points on said other surface and saidthin film and chip attached to one another so as to form a chip module;and a substrate for said chip having a pattern of connection padsmatching the pattern of connection pads on said one surface of said thinfilm with corresponding pads in each of said patterns electricallyconnected to one another.
 9. The chip package of claim 8 wherein saidthin film is a polymer.
 10. The chip package of claim 8 wherein saidthin film is attached to said chip with an epoxy underfill.
 11. The chippackage of claim 10 wherein said thin film is attached to said substratewith a spacer.
 12. The chip package of claim 10 wherein said thin filmis attached to said substrate with a reworkable underfill.
 13. The chippackage of claim 10 wherein a plurality of chip modules are formed onsaid substrate.
 14. The chip package as set forth in claim 13 whereinsaid substrate is a PCB.
 15. The chip package as set forth in claim 13wherein said substrate is a chip carrier.
 16. The chip package as setforth in claim 15 wherein said chip carrier is mounted on a PCB.
 17. Thechip package as set in claim 8 wherein said flexible redistribution filmis formed directly on said chip to form said chip module.
 18. The chippackage as set forth in claim 8 wherein said flexible redistributionthin film layer is formed directly on a wafer and said wafer is diced toform said chip module.
 19. A method of forming a chip module comprising:forming a flexible redistribution thin film having multiple layers ofredistribution metallurgy on a temporary substrate; forming an array ofpads on one surface of said thin film matching the array of pads on saidchip; forming another array of pads on the other surface of said thinfilm matching the array of pads on the substrate to which it will beattached for packaging; attaching said chip pads to the respective padson said one surface of said thin film; and removing said thin film andchip from said temporary substrate to thereby form said module.
 20. Themethod of claim 19 wherein said temporary substrate is glass.
 21. Themethod of claim 20 wherein said glass is a boro float glass.
 22. Themethod as set forth in claim 19 wherein said step of attaching said chipto said thin film includes attaching said chip to said thin film bysolder ball connections.
 23. the method as set forth in claim 22 whereinsaid space between solder balls connections is filled with an epoxybefore removal from said temporary substrate.
 24. The method as setforth in claim 23 wherein said step of removing said thin film and chipfrom said temporary substrate includes release by laser ablation throughsaid glass.
 25. The method as set forth in claim 24 wherein said laseris a 308 nm HeNe laser.
 26. The method as set forth in claim 19 whereinsaid film comprises alternate layers of polyimide and circuitry toprovide both a redistribution medium for signal and power redistributionfrom chip to packaging substrate and a compliant medium to providerelief to stress on electrical connections caused by thermal mismatchbetween chip and substrate.
 27. A wafer scale method of forming chipmodules, comprising: forming a flexible redistribution thin filmdirectly on a wafer by depositing alternate layers of a flexibleinsulating material and conductive metallurgy; and forming metal filledvias in said layer flexible insulating material to interconnect saidlayers of metallurgy to one another and to connection pads on said chipso as to form a power and signal redistribution thin film for said chipand; forming vias in the final layer of insulating material having apattern matching the pattern of the substrate to which it is to beattached; forming a pattern of pads on said vias in said final layer ofinsulating material; and dicing said wafer to form chip modules readyfor packaging.
 28. The method as set forth in claim 27 wherein saidflexible insulating material is polymer.
 29. The method as set forth inclaim 27 wherein said pads are BGA pads.
 30. A wafer scale method offorming chip modules, having flexible thin film redistribution layerthereon comprising: depositing a thin layer of insulating materialdirectly on said wafer; forming vias in said layer of insulatingmaterial to the chip electrical contacts on said wafer; filling saidvias with a conductive material: forming a metallurgical pattern on saidthin layer of insulating material and in contact with said conductivematerial of said vias; alternating said steps of forming layers ofinsulating material with metal filled vias and forming saidmetallurgical patterns on said layer of insulating material to therebyform a selected redistribution pattern for chip signal and powerredistribution; forming a pattern of metal filled vias in the finallayer of insulating material matching the pattern of contact pads on thesubstrate to which said chip modules will be attached; forming pads onsaid metal filled vias of said final layer of insulating material; anddicing said wafer to form said chip modules.
 31. The method as set forthin claim 30 wherein said flexible insulating material is a polymer. 32.The method as set forth in claim 30 wherein said pads are BGA pads.